This invention relates to a process for fabrication of Insulated Gate Field Effect Transistors (IGFETs) and, more specifically to short-channel enhancement mode IGFETs.
It is well known in the art that the frequency response or switching speed of an IGFET improves as the channel length and parasitic capacitances of the IGFET are reduced in magnitude. The reason for this is that a reduction in channel length reduces the transit time for carriers travelling between source and drain, while a reduction in the parasitic capacitances decreases the time required for charging and discharging the capacitances. Double-diffused metal oxide semiconductors (D/MOS) such as the one described in Cunningham et al U.S. Pat. No. 3,996,655, are short-channel IGFETs with reduced parasitic capacitances. In a typical N- channel D/MOS type device, a substrate with very low .pi. type impurity concentration has source and drain regions having an N+ type impurity diffused therein in the typical MOS fashion. What is distinguishing about the D/MOS construction is that the N+ source region is set within a larger and deeper diffusion of P- impurity which effectively provides a narrow P- type channel adjacent to the source, while the .pi. type region between the P-type diffusion and the N+ type drain diffusion functions as a drift region.
With this D/MOS construction, very short channel lengths are realizable by properly controlling the N+ and P- diffusions in and around the source region. Furthermore, in a D/MOS the parasitic drain-to-substrate capacitance is smaller than a conventional short-channel MOS device, because the N+ drain diffusion of the D/MOS is surrounded by the substrate having a very low .pi. type impurity. However, the P-channel diffusion around the source diffusion still maintains the substantial capacitance at the periphery of the source region just as in a conventional FET. Furthermore, for reasons that will be discussed later in the description, the threshold voltage of a D/MOS varies considerably from unit to unit.